The instruction sets within computer system architectures are often expanded with new instructions. The additional new instructions usually provide some needed functional capability, or an improvement in performance over some prior method. As these new instructions are developed, many times they are added only to the newest model computers that support the architected instruction set and not to previous, existing models. This can create problems for users of these computers who develop software programs for execution on these computers. These software developers desire to use the very latest instructions in order that their programs provide the most function, or perform the most quickly. Many times these developers need their programs to be able to execute on many (or all) models of the computer hardware. However, if a new instruction is coded in a program, and execution is attempted on an older model computer that does not support this instruction, the processor does not recognize the operation code (op-code) of the instruction and causes an error exception to occur. Detecting invalid op-codes is well known in the art, for example, U.S. Pat. No. 4,167,778, INVALID INSTRUCTION CODE DETECTOR, issued Sep. 11, 1979, by Ralph E. Sipple, which describes detecting an invalid (undefined) operation code at instruction decode time and then causing an error signal. Computer hardware systems, e. g., the IBM ESA/390 computing system, typically provide a mechanism for an exception handling program to gain control upon the error exception (for example in the IBM ESA/390 architecture this is achieved via a Program Status Word (PSW) for an interrupt category, and the address (in the PSW) of the proper interrupt handler). Many operating systems executing in these processors also provide a recovery mechanism based on the processor's exception handling capability. For example, in IBM's MVS/ESA operating system the capability exists for a program to specify a recovery routine (program) to begin execution if an error exception occurs. The recovery routine (program) can recover from the error, and continue execution, or allow the error exception to terminate execution of the program. This creates a dilemma for the software developer if the new instructions are not available on all models; the program can fail depending on the computer model executing the program. Typically, the dilemma is handled in one of three ways;
1. The program is written to establish a recovery routine (program) to receive control when the program attempts to execute the potentially undefined instruction. Upon receiving control, the recovery routine simulates the undefined instruction's execution and the program continues at the next sequential instruction (NSI) after the program interruption. PA1 2. Separate versions of the program are written. The version that includes the new instruction is specified as the version for the computer models supporting the new instruction. The version that does not include the new instruction is specified for computer models that do not support the new instruction. PA1 3. The program is written without using the new instruction, thus insuring it's execution on all models of the computer, but not gaining the benefits of the new instruction on those models supporting the new instruction.
There are shortcomings with each of these alternatives. Alternative one (1) works on both processors that do not support the new instruction, and processors that do support the new instruction. However, this alternative can result in significant performance degradation when executing on older processors that do not support the new instruction. Simulation of these new instructions, which typically are implemented for performance enhancements, introduce exception handler and recovery program overhead to already performance sensitive areas. This tends to make a bad situation worse when executing on older processors which do not support the new instructions and leads to alternatives two (2) and three (3). Alternative two (2) adds additional cost to developing and maintaining the program, since multiple versions exist. It can also create confusion if an incorrect version is executed and that version abnormally terminates, or fails to provide the enhanced function. Alternative three (3) affords the program no benefit from the new instruction and therefore no benefit to the users of the newer computer model. While alternative one (1) appears to remedy the situation, it does so by incurring the overhead of the computer system's exception handling mechanism and the operating system's recovery processing before determining that simulation is necessary, because it requires that execution of the undefined instruction be attempted. There are examples, in prior art, of interrogating an element of a computer system to determine if the computer system element supports a specific function before attempting execution of that function. For example, the IBM Technical Disclosure Bulletin, dated December 1991, Vol. 34, No. 7A, pp. 122-131, titled "NEW I/O SUBSYSTEM COMMAND: READ COMMAND SET", by R. E. Wagner, which describes a new command to an I/O Subsystem requesting feedback of all commands supported by that I/O Subsystem, so that an attempt to execute a nonexistent function is avoided. This technique of responding with all functions that are supported is not well suited for use in program to CPU communication. Because of the need for very fast interrogation and response, while executing instructions on a processor, a high performance specific query is needed. In the I/O subsystem world it is common for I/O driver software to have the need, at initialization time, for general information about the subsystem to which it is connected. But, during execution of programs, any extra CPU cycles become counterproductive. Additionally, a nonspecific response, such as the one described above in the referenced TDB, would generally be unusable for implementation in most programs as it would add a great amount of logic to each program to maintain lists of instructions that are supported and then to have to search lists looking for an instruction that may not be there. What is needed in the processor environment is a high performance, easy to implement method of determining if an instruction is supported. There are also many examples, in prior art, of "pre-fetching" and interrogating instructions prior to their execution. The IBM Technical Disclosure Bulletin, dated November 1980, pp. 2600-2604, titled "INSTRUCTION SCAN FOR EARLY RESOLUTION OF A BRANCH INSTRUCTION", by J. Y. Yamour, which describes a means of "pre-fetching" and interrogating instructions to search for specific "branch" op-codes, so that the instruction stream to be executed after the branch instruction can be determined. This is done to improve performance of a "cached" CPU. Likewise, U.S. Pat. No. 4,710,866, METHOD AND APPARATUS FOR VALIDATING PREFETCHED INSTRUCTION, issued Dec. 1, 1987, by John Zolnowsky, et al., which describes "pre-fetching" instructions in a pipelined CPU and interrogating the instructions in order to insure that complete instructions have been fetched. In so doing, this patent also identifies undefined instructions at "pre-fetch" time but, unlike the present invention, takes no action to inform the executing program of this fact so that the program could avoid executing them. Instead, it leaves them for execution and processing through an aforementioned interrupt (exception) processor, thus defeating the present invention's objective of avoiding execution overhead.